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FA13842,13843,13844,13845
s Description
The FA1384X series are CMOS current mode control ICs for off-line and DC-to-DC converters. These ICs can reduce start-up circuit loss and are optimum for high efficiency power supplies because of the low power dissipation achieved through changes in the CMOS fabrication process. These ICs can drive a power MOSFET directly. The high-performance, compact power supply can be designed with minimal external components .
CMOS IC FA13842, 13843, 13844, 13845 For Switching Power Supply Control
s Dimensions, mm SOP-8
8 5
1
4 4.9
+0.1 -0.05
s Features
* * * * * * * CMOS process Low-power dissipation Standby current 2A (max.), start-up current 30A (max.) Pulse-by-pulse current limiting 5V bandgap reference UVLO (Undervoltage lockout) with hysteresis Maximum duty cycle FA13842, 13843: 96% FA13844, 13845: 48% * Pin-for-pin compatible with UC384X
Note: Pins are fully compatible, but characteristics are not. When our ICs are applied to a power supply circuit designed for other manufactures' 384X series, the characteristics and safety features of the power supply must be checked.
6.00.2
3.9
0.40.1
1.270.2
DIP-8
8 5
s Types of FA1384X series
Type UVLO Start threshold Stop threshold FA13842P 16.5V1V 9V1V FA13842N FA13843P 9.6V1V 9V1V FA13843N FA13844P 16.5V1V 9V1V FA13844N FA13845P FA13845N 9.6V1V 9V1V Maximum duty Package cycle 96% DIP SOP 96% DIP SOP 48% DIP SOP 48% DIP SOP
1
9.3 1.5
4
6.4
3.0min 4.5max
3.3
0~8
0.05 0.25 -
+0.1
7.62
2.540.25
0.460.1
0~15
0~1
5
1.7max
0.20
1
FA13842, 13843, 13844, 13845
s Block diagram
FA13842, 13843
VCC 7 30V UVLO
OUTPUT ENB
Pin No. Symbol Function 1 COMP Compensating
UVLO
VCC 5V REF ENB 2.5V 8 VREF
2 3 4
FB ISNS RT/CT
6 OUT
RT/CT 4 ER AMP FB 2 COMP 1 ISNS 3 2R 1R
OSC
5 GND
1V
SQ FF R QB
5 6 7 8
GND OUT VCC VREF
5V Controlled block
FA13844, 13845
VCC 7 30V UVLO
OUTPUT ENB
Description Error amplifier output, available for loop compensation circuit Feedback Inverting input of the error amplifier Current sensing Input voltage proportional to inductor current Oscillator control Setting oscillation frequency and maximum duty-cycle with resistor RT and capacitor CT Ground Ground Output Output for driving a power MOSFET Power supply Power supply Reference voltage Reference voltage and current source charging capacitor CT through resistor RT
UVLO
VCC 5V REF ENB 2.5V
8 VREF
6 OUT
RT/CT 4 ER AMP FB 2 COMP 1 ISNS 3 2R 1R
OSC
5 GND
1V
SQ FF R QB
TFFQ CLK QB
5V ControlIed block
s Absolute maximum ratings (Ta=25C)
Item
Supply voltage Zener current Output peak current FB/ISNS terminal input voltage Error amplifier sink current Total power dissipation Thermal resistance Junction temperature Ambient temperature Storage temperature Symbol VCC IZ IO VIN ISINK Pd R j-a Tj Ta Tstg Test condition Low impedance source Zener clamp (Icc<10mA) Source current Sink current FB, ISNS at Ta < 50C Junction-air DIP SOP DIP SOP Rating 28 Self limiting 10 400 1 -0.3 to 5.3 10 800 400 125 250 150 -25 to 85 -40 to 150 Unit V V mA mA A V mA mW C/W C C C
2
FA13842, 13843, 13844, 13845
s Recommended operating conditions
Item Supply voltage Oscillation timing capacitor Oscillation timing resistor Oscillation frequency Symbol VCC CT RT fOSC Min. 10 0.47 2.0 10 Max. 25 10 100 500 Unit V nF k kHz
s Electrical characteristics (Vcc=15V, RT=10k, CT=3.3nF, Ta=25C) Reference voltage section
Item Reference voltage Line regulation Load current regulation Temperature regulation Output current at short-circuit Symbol VREF LINE LOAD VTC IOS Test condition Tj=25C, IL=1mA Vcc=10 to 25V IL=0 to 20mA Ta=-25 to 85C Tj=25C Min. 4.75 Typ. 5.00 3 3 0.3 60 Max. 5.25 20 25 Unit V mV mV mV/C mA
Oscillator section
Item Oscillation frequency Voltage stability Temperature stability Oscillation amplitude Discharge current Symbol fOSC fdv fdt VOSC IDISCHG Test condition Tj=25C Ta=-25 to 85C Vcc=10 to 25V Ta=-25 to 85C Tj=25C Tj=25C Min. 49 47 Typ. 52 0.25 -0.07 1.6 8.4 Max. 55 57 1 Unit kHz kHz % %/C V mA
Error amplifier section
Item Input voltage Input leak current Open-loop gain Unity gain bandwidth Output source current Output sink current Output voltage Symbol VFB IFB AV fT ISOURCE ISINK VH COMP VL COMP Test condition COMP=2.5V, Tj=25C Min. 2.4 65 0.7 -0.8 2 4.0 Typ. 2.5 72 1 -1.0 15 4.5 80 Max. 2.6 2 Unit V A dB MHz mA mA V mV
FB=2.3V, COMP=0V FB=2.7V, COMP=1V FB=2.3V, RL=15k to GND FB=2.7V, RL=15k to VREF
500
Current sensing section
Item Voltage gain Maximum input signal Input bias current Delay to output Symbol AV IS VTH IS IIS TPD Test condition Tj=25C FB=0V Tj=25C, ISNS to OUT Min. 2.85 0.9 Typ. 3 1.0 -1 150 Max. 3.15 1.1 -5 300 Unit V/V V A ns
3
FA13842, 13843, 13844, 13845
Output section
Item High-level output Low-level output Rise time Fall time Symbol VOH VOL tr tf Test condition I source=-20mA I source=-100mA I sink=20mA I sink=200mA CL=1nF, Tj=25C CL=1nF, Tj=25C Min. 14.5 12 Typ. 14.75 13.5 0.15 1.5 40 20 Max. Unit V V V V ns ns
0.3 3 150 150
Under-voltage lockout section
Item Start threshold Min. operating voltage Hysteresis Symbol VTH ON VTH OFF VHYS Test condition FA13842, 13844 FA13843, 13845 FA13842, 13844 FA13843, 13845 Min. 15.5 8.6 8 Typ. 16.5 9.6 9 7.5 0.6 Max. 17.5 10.6 10 Unit V V V V V
PWM section
Item Maximum duty cycle Minimum duty cycle Symbol Dmax Dmin Test condition FA13842, 13843 FA13844, 13845 FB=5V, COMP=Open Min. 94 47 Typ. 96 48 Max. 98 50 0 Unit % % %
Overall device
Item Standby current Start-up current Operating current Zener voltage (Vcc) Symbol ICCL ICC ST ICC OP VZ Test condition FA13842, 13844 Vcc=14V FA13843, 13845 Vcc=7V Vcc=Start threshold Icc=5mA Min. Typ. Max. 2 2 30 5 34 Unit A A A mA V
28
12 3 30
4
FA13842, 13843, 13844, 13845
s Characteristic curves (Ta=25C) Timing resistance vs. oscillation frequency FA13842, FA13843
100
Output dead time vs. oscillation frequency FA13842, FA13843
100 VCC= 15V Ta= 25C 470pF 2.2nF CT=10nF 10
2.2nF CT=10nF RT resistance (k)
470pF Output dead time (%)
10
VCC= 15V Ta= 25C 1 1 10 100 Oscillation frequency (kHz) 1000
1
10
100 Oscillation frequency (kHz)
1000
Timing resistance vs. oscillation frequency FA13844, FA13845
100 470pF 2.2nF
Output dead time vs. oscillation frequency FA13844, FA13845
100 VCC= 15V Ta= 25C 90
Output dead time (%)
CT=10nF RT resistance (k)
80
10
70 2.2nF CT=10nF 60
470pF
VCC= 15V Ta= 25C 1
50
40 1 10 100 Oscillation frequency (kHz) 1000
10
100 Oscillation frequency (kHz)
1000
RT/CT discharge current vs. temperature
10
Output max. duty cycle vs. timing resistance FA13842, FA13843
100 Output maximum duty cycle (%) 90 80 70 60
RT/CT discharge current (mA)
9.5
9
8.5
8
7.5
50 40
7 -50
0
50 Temperature (C)
100
150
1
2 5 RT timing resistance (k)
10
5
FA13842, 13843, 13844, 13845
ISNS threshold voltage vs. COMP voltage
1200 VCC= 15V FB= 0V OUT= off COMP source current (A) 0 1 3 2 COMP voltage (V) 4 5
COMP source current vs. COMP voltage
0
1000 ISNS threshold voltage (mV)
-200
800
-400
600
-600
400
-800
200
-1000
0
-1200
0
1
3 2 COMP voltage (V)
4
5
COMP to ISNS offset voltage vs. temperature
2.5
COMP source current vs. temperature
-800 VCC= 15V COMP= 0V
COMP to ISNS offset voltage (V)
2 COMP source current (A) 0 50 Temperature (C) 100 150
-900
-1000
1.5
-1100
1
-1200
0.5
-1300 0 -50
-1400 -50
0
50 Temperature (C)
100
150
Error amp open loop voltage gain and phase vs. frequency
100 80 60 40 Gain 20 0 -20 -40 10 180 Phase Phase ( ) 0
VREF short circuit current vs. temperature
80 VCC= 15V VREF= 0V VREF short circuit current (mA) 70
Open loop voltage gain (dB)
60
50
40
30
100
1.0k
10k 100k Frequency (Hz)
1.0M
10M
20 0 50 Temperature (C) 100 150
6
FA13842, 13843, 13844, 13845
VCC supply current vs. VCC supply voltage
8 7 6 VCC current (mA) 5 4 3 2 13843/45 1 0 RT= 10k CT= 3.3nF OUT= No load VCC startup current (A) 14 Ta= 25C 12 10 8 6 4 2 0 14
VCC startup current vs. VCC supply voltage FA13842, FA13844
13842/44
0
10
20 VCC voltage (V)
30
14.5
15
15.5 16 VCC voltage (V)
16.5
17
Output waveform
Vcc=15V, OUT CL=1nF, Ta=25C Vcc=15V, OUT CL=2.2nF, Ta=25C
VCC= 15V OUT CL= 1nF Ta= 25C
VCC= 15V OUT CL= 2.2nF Ta= 25C
2.50V
25.0ns
2.50V
50.0ns
7
FA13842, 13843, 13844, 13845
s Description of each circuit
1. Oscillator The oscillation frequency is determined by timing resistance RT and timing capacitor CT, which are connected to RT/CT terminal. CT is charged to about 3V through RT from a 5V reference, and discharged to about 1.4V by the built-in discharge circuit. (See Fig. 1, 2, 3.) Blanking pulses are generated in the IC during the CT discharge period. The output is fixed in the "low" state by these pulses, and a fixed dead time is produced. See the characteristic curves on page 45 for the oscillation frequency, RT and CT. In the case of FA13844/45, a flip-flop causes the output to be blanked with every other cycle. Therefore, the switching frequency of a power MOSFET is 1/2 of the oscillation frequency determined by RT and CT. (See Fig. 3.)
Vcc Vin
VCC
7
30V
UVLO
ENB 2.5V
OUTPUT ENB
6
OUT
RT RT/CT CT
4 5 GND
RS OSC
ER AMP 2R 1R
FB 2 COMP 1 ISNS
3
1V
SQ FF R QB
2. Error amplifier Inverting input and output are connected to the FB terminal and COMP terminal, respectively. A 2.5V reference is connected internally to the non-inverting input. The output voltage is offset by a diode VF voltage (=0.7V) and divided by three. The divided voltage is connected to the input of the current sensing comparator.
Fig. 1
3V CT 1.4V
3. Current sensing comparator and PWM latch The "High" state of the OUT terminal begins at the time CT starts charging. The OUT terminal turns to "Low" when the peak inductor current reaches the threshold level controlled by the error amplifier output (COMP terminal). The inductor current is converted to a voltage by sensing resistor RS inserted between GND and the source of a power MOSFET. This voltage is monitored by the ISNS terminal. The peak current of inductor "Ipk" is expressed as follows: 0.7V VF Ipk=(Vcomp-0.7) / (3*RS)
Vcomp: a voltage on COMP terminal
Set
COMP ISENS Reset
OUT
The maximum value of the threshold level of the current sensing comparator is held to 1V. Therefore, the maximum peak current "Ipk(max)" is as follows: Ipk(max)=1.0V/RS
CT
Fig. 2
FA13842, 13843
3V
4. Undervoltage lockout (UVLO) In order to set the IC in the operation mode before the output stage(OUT terminal) is enabled, two under-voltage lockout comparators are incorporated to monitor the power supply voltage (VCC) and reference voltage (VREF). The threshold level of the VCC comparator is set at 16.5V/9V for FA13842/44 and 9.6V/9V for FA13843/45. In the standby mode, in which the VCC is under ON threshold, the power supply current is maintained at nearly 0 (zero). However, a maximum current of 30A is required to change from standby mode to operating mode . The threshold level of the VREF comparator is set at about 3.2V/ 2.0V. A 30V zener diode is connected to VCC and GND to protect the IC against overvoltages.
1.4V Set
COMP ISENS Reset
OUT
Fig. 3
FA13844, 13845
8
MOSFET
UVLO
VCC 5V REF
8
VREF
FA13842, 13843, 13844, 13845
DB ~ AC INPUT
5. Output stage An output stage of CMOS inverter composition is incorporated, thereby making it possible to fully swing the gate voltage of a power MOSFET to the VCC. The output stage provides a source current of 400mA and a sink current of 1A as the peak current capacity. (When VCC is 15V) The output stage is held in the "Low" state in standby mode.
+ + C1
T1
~ R1 D1 + C2
7
6. Reference voltage The 5.0V(5%) bandgap reference(Tj=25C) is built-in. It is possible to supply a current of about 10mA to an external circuit in addition to supplying a charge current to the timing capacitor of the oscillator. (See characteristic curve on page 46.) Connect a ceramic bypass capacitor of 0.1F or higher to the VREF terminal to stabilize this voltage.
FA13842
6
MOSFET
Rs
Fig. 4
4 Start-up time[sec]
C2=47F
Input:100V AC C2=22F
s Design advice
1. Start-up circuit A typical start-up circuit is shown in Fig. 4. The AC INPUT voltage charges capacitor C2 and supplies start-up current to the IC through start-up resistance R1. When this voltage reaches the ON threshold voltage, the IC reverts to the operation mode and electric power is supplied from the bias winding of the transformer thereafter. Using CMOS process, the start-up current is less than 30A. When the start-up resistance is increased, the charging rate of capacitor C2 decreases and start-up time increases. Select the optimum values for R1 and C2. The relation between the start-up resistance and start-up time for the circuit indicated in Fig. 4 is shown in Fig. 5. Fig. 6 indicates a method to increase the start-up resistance to reduce loss and shorten start-up time. The start-up time is shortened by reducing the capacitance of C2. The bias current is supplied from C3 after start-up.
3 2 C2=10F 1 0 0 200 800 400 600 Start-up resistance R1 (k) 1000 1200
Fig. 5
Start-up time
R1 D1 + C2
7
D2 + C3
FA13842
6
2. Synchronized operation with external signals The circuit shown in Fig. 7 allows synchronized operation with external signals. Synchronized operation is started when the RT/CT terminal voltage is raised to about 3V or higher. (Synchronized at leading edge.) The external synchronizing signal should be higher than the free-run frequency. In the case of FA13844/45, the output frequency of the OUT terminal is 1/2 that of the synchronizing signal frequency.
RT
Fig. 6
8
REF
Synchronized
4
OSC
C4
CT R2
2
+ ER AMP
2R 1R
D3
1
5
Fig. 7
9
FA13842, 13843, 13844, 13845
3. Latched shutdown A typical circuit for latched shutdown is shown in Fig. 8. The voltage of the OUT terminal is kept low if the voltage of the COMP terminal is low. The voltage of the COMP terminal must be set at 0.7V or less in the application temperature range. (See characteristic curve on page 46 "COMP to ISNS offset voltage vs temperature".) The source current from the COMP terminal is less than about 1.3mA. Use of a thyristor such as that shown in Fig. 9 is not effective because the saturation voltage of the thyristor is higher than 0.7V. When a thyristor is used, increase the voltage of the FB terminal to more than 3V as shown in Fig.10. In the case of a latched shutdown, it is necessary to supply a current larger than the hold current of the thyristor structure circuit or of the thyristor. This current should be provided through a start-up resistor from the AC input.
DB ~+ AC INPUT ~ R1 D1 + C2 + C1 MOSFET T1
7 8
REF 30V
4
OSC
Latched shutdown with a thyristor using the COMP terminal is not effective.
2
+ R4 Latching signal Tr2 D4
1
2R 1R
ER AMP
Tr1 R3
5
Fig. 8
7 8
7
REF 30V
8
REF 30V
4
OSC + 2R 1R
Latching signal SCR2
4
OSC + 2R 1R
2
2
ER AMP Latching signal SCR1
1
ER AMP R5 C5 1
5
5
Fig. 9
Fig. 10
10
FA13842, 13843, 13844, 13845
3-1 The method of detecting an overvoltage (detection on primary side) A typical latched shutdown circuit to protect against overvoltages detected on the primary side is shown in Fig. 11. When the secondary voltage increases in the flyback circuit, the voltage of the bias winding also increases in proportion. When this voltage increase is detected by zener diode ZD1, a latched shutdown is accomplished. As the secondary voltage is detected through a transformer, detection accuracy is low. 3-2 The method of detecting an overvoltage (detection on secondary side) A typical latched shutdown circuit to protect against overvoltages detected on the secondary side is shown in Fig. 12. The detected voltage accuracy is high compared to overvoltage detection on the primary side. 3-3 The method of detecting an overcurrent (detection of primary current) A typical primary overcurrent detection circuit is shown in Fig. 13. 3-4 The method of detecting an overcurrent (detection of secondary current) A typical secondary overcurrent detection circuit is shown in Fig. 14.
DB ~+ AC INPUT ~ R1 D1 + C2
7
T1 + C1
D6 + C7
R9 ZD2 MOSFET
R6
FA13842
1
6
PC1 Rs R8
R4 Tr2 Tr1 C6 R3 D5 R7
PC1
Fig. 12
DB ~+ AC INPUT ~ R1 R6
7
T1 + C1
D1 + C2
DB ~+ AC INPUT ~ R1 D1 R6
7
T1 + C1 R4 Tr2 + C2 Tr1 R3 MOSFET
6
FA13842
1 3
6
MOSFET R12
D5 Rs R11 Tr3 C8 R10
C6
ZD1
FA13842
1
Fig. 13
Rs DB ~+ AC INPUT + C1 ~ T1 D6 + C7 Tr4 R13
Tr2
R4 D5 Tr1
R3
C6
Fig. 11
R6
R1
D1 + C2
7
R14
PC1 MOSFET R15 Tr5 Rs R16
FA13842
1
6
R4 Tr2 Tr1 C6 R3 D5 R7
R8 PC1
Fig. 14
11
FA13842, 13843, 13844, 13845
4. Soft start A soft-start circuit is shown in Fig. 15. An aproximate soft-start time is determined with the following calculation. This soft-start time is defined as the time the ISNS terminal threshold voltage increases from 0V to 1V. tsoft-start [ms]=4.3*C9[F] 5. Suppression of noise at the current sensing terminal As each cycle current value is monitored in the current mode control, there is the possibility that a malfunction will occur even with a relatively low noise level. Therefore, it is necessary to add a CR filter to reduce the level of noise at the current sensing terminal. (See Fig. 16.) 6. ON/OFF circuit with an external signal A typical ON/OFF circuit is shown in Fig. 17. The output stage (OUT terminal) is enabled when the voltage at the FB terminal is reduced to less than 2.0V and is disabled when the FB terminal voltage increases to more than 3V. Set the voltage of the FB terminal at a maximum of 5.3V in this case.
8
REF
4
OSC 1mA ER AMP 2R
+ D7 R17 1M D8 C9
2
1R
1 5
Fig. 15
DB ~ AC INPUT ~
+ + C1
T1
MOSFET
6
FA13842
3
R18 C10 Rs
Fig. 16
7 8
REF 30V
R19
4
OSC + 2R ER AMP
2
ON/OFF signal Tr6
1
1R
5
Fig. 17
12
FA13842, 13843, 13844, 13845
7. Feedback circuit 7-1 A method that does not use an internal ER AMP A method that does not use an internal ER AMP is shown in Fig. 18. Connect the FB terminal to GND and connect an optocoupler to the COMP terminal of the ER AMP output for feedback control. It is possible to obtain a precise power supply output voltage, because the output voltage is monitored directly on the secondary side. Be sure to connect the FB terminal to the GND in this case. There is the possibility of a malfunction occuring if the FB terminal is open. 7-2 A method using an internal ER AMP A method using an internal ER AMP is shown in Fig. 19. In the flyback circuit, the bias winding voltages of the transformer are proportional to the secondary winding voltage. Therefore, VCC is approximately proportional to the DC output voltage on the secondary side. VCC is divided by resistors and monitored at the FB terminal to control the output voltage. This feedback circuit consists of a minimal number of external components. However, regulation of the DC output voltage is poor because the output voltage is not monitored directly.
T1 + C1 D6 C7 +
MOSFET C11 PC2 R19
3 1 2
R20 2R + 2.5V R + R18 R21 Rs PC2
R22
C12
C10 R23
Fig. 18
T1 + R1 D1 C1
D6 + C7
8. Slope compensation It is well known that a current mode converter that controls peak current can oscillate irregularly when the inductor current is continuous and the duty cycle is greater than 50%. This irregular oscillation is called subharmonic oscillation. The period of subharmonic oscillation is equal to the integral number of the switching periods. This phenomenon is shown in Fig. 20. Lu indicates the positive slope of the inductor current. The slope is determined by the input voltage and the primary inductance value of the transformer. -Ld indicates the negative slope, which is determined by the rate of energy discharge to the secondary side. Fig. 20 shows the inductor current waveform when T reveals the oscillation period and Is reveals the control signal of the peak inductor current. TON and TOFF vary even when having the same T, Is, Lu and -Ld. If it is assumed in Fig. 21 that the inductor current varies iL at t0, the variation iL' of the inductor current at t1 is larger than iL at t0. Thereafter, this inductor current variation gradually increases, and as a result, subharmonic oscillation occurs.
R26 C13 R25
2 1
+ C2
2R + 2.5V R + R18 MOSFET
R24
3
C10
Rs
Fig.19
Is Lu TON -Ld TOFF
T
T
T
T
Fig. 20
Diverge iL iL
to
t1
Fig. 21
13
FA13842, 13843, 13844, 13845
Fig. 22 illustrates a case when the inductor current variation iL' at t1 is smaller than iL at t0. In this case, inductor current variations gradually converges and the inductor current becomes stable. It is necessary to apply slope compensation to the control signals in order to prevent such subharmonic oscillations when the inductor current is continuous and the duty cycle is greater than 50%. The waveform of the inductor current when slope compensation is applied is shown in Fig. 23. Slope compensation adds the negative slope of inclination -Kc to the control signal of the inductor peak current. iL' shows the variation of the inductor current at t1 when slope compensation is not applied, and iL' s shows the variation of the inductor current at t1 when slope compensation is applied. Thus, iL' can be changed by -Kc, and IL' s becomes smaller when -Kc is large. It is necessary to apply slope compensation to satisfy the equation iL iL's, that is, I -Kc I I -1/2 Ld I as the condition which achieves stable operation. Typical circuits are shown in Fig. 24 and 25.
Converge iL iL
to
t1
Fig. 22
Is -Kc iL iL Lu -Ld iLs Compensated Ton T to t1
Fig. 23
Vcc
Vin
VCC
7
RT Tr7 R27 CT Output R25 R24 RT/CT
4
Vcc 5VREF ENB 2.5V
OUTPUT ENB
8 6
30V
UVLO
OUT R18 C10
Rs
FB 2 R26 C13 COMP ISNS
1 3
ER AMP 2R 1R
OSC 1V
5 GND
SQ FF R QB
Fig. 24
Vcc
Vin
VCC
7
RT Tr7 R27 CT Output RT/CT R25 FB R24 R26 C13 COMP ISNS
4 2 1 3
30V
UVLO
Vcc 5VREF ENB 2.5V
OUTPUT ENB
8
6
OUT R18 C10
Rs
ER AMP 2R 1R
OSC 1V
5 GND
SQ FF R QB
Fig. 25
14
MOSFET
UVLO
VREF
MOSFET
UVLO
VREF
FA13842, 13843, 13844, 13845
s Application circuit
DB
~+
T1
+ C1 400V/220F
L1 YG902C D6 4700F 2 3.3H
AC80~264V
~
C16 0.022F D9 ERA22-10
R27 100k C7
+ + C17
16V 0~4A
C18 1000F GND
+
R1
560k MOSFET 2SK2101 R30 33 R31 100 RT 8.2k VCC FA13842
7
C15 470pF D10 ERA22-10 Rs 0.33 R28 1k PC2 R20 1.2k R32 R21 2.2k 10k R22 560
R29 4.7k D11 ERA91-02
C2 22F
VCC 5VREF ENB 2.5V
OUTPUT ENB
IC
UVLO 30V UVLO
8 6
VREF OUT
+
C12 0.1F VR1 5k
D1 ERA91-02
COMP RT/CT CT 2200pF
1
C11 1000pF FB 2 PC2 R19 1k ISNS3
4
2R 1R
OSC 1V
SQ FF R QB
5
GND
C10 100pF
R18 1k
C14 0.1F
Parts tolerances characteristics are not defined in the circuit design sample shown above. When designing an actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical operation.
15

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